The present invention relates, in general, to current sharing control circuits and, more particularly, to direct duty cycle current sharing control circuits.
Current sharing control circuits are typically employed to provide a method whereby several power supplies arranged in parallel provide substantially equal amounts of current to their respective loads. An example of such an arrangement can be found with advanced computer motherboards. Computer motherboards typically contain a central processing unit (CPU), random access memory (RAM) and various peripheral input/output (I/O) capability. Some of the more advanced computer motherboards contain several CPU""s for parallel processing, but require a substantial amount of power in return. Each CPU can require as much as 60 amps of current, or more, from the respective power supply voltage input.
In order to supply current to multiple CPU""s within the computer, manufacturers have begun to employ multiple voltage regulators operating from a common input voltage supply, arranged in parallel, to supply the high current demands of a multiple CPU load. Regulations governing computer hardware suppliers require multiple voltage regulators arranged in parallel to boost output current drive, to supply current to the load in substantially equal proportion. In order to comply with substantially equal current load regulations, prior art current sharing circuits have been developed. Prior art current sharing techniques typically employ a standard pulse width modulated (PWM) buck converter along with a current sensor to monitor the output current load of each regulator. The current sense information is used to promote current sharing between the parallel connected regulators. Current sharing techniques, however, employed by prior art current sharing circuits, modify either the feedback signal or the reference signal in response to the output current sense to accomplish current sharing. A problem with this technique occurs at start up, when the PWM controllers are not yet operating in regulation. Attempts to promote current sharing among the regulators fail, since current sharing is not possible until the PWM controller is in regulation. PWM controllers typically employ soft start circuitry which limits the duty cycle of the PWM drive signal to a minimum value to avoid saturation or damage at start up. Typical soft start times are on the order of tens to hundreds of milliseconds. During soft start, the prior art current sharing circuits fail to promote current sharing, since the PWM controllers are not operating in regulation. The regulator with the fastest soft start rate will, therefore, attempt to provide the total load current and either trigger an over current condition or cause system failure.
A need exists, therefore, for a current sharing control circuit that promotes current sharing at any stage of operation from start up to power off.